Design/BFM (Bus functional Model) development in system Verilog, knowledge on IO interactions
C, Perl Scripting knowledge
System Verilog assertion (SVA) knowledge
Experience in working in OVM environment
Experience in Scoreboard/monitor/coverage collector development
Experience in Design Specification interpretation to come up with Testplan, can write Test from that Testplan written in system Verilog using randomization
Excellent debug skills. Can work independently - require minimum supervision.
Experience in working with VCS simulator
7 to 10 years of working experience
Clear in CommunicationShould understand RTL verilog, should be proficient in Debug, Should know how to develop test infrastructure and tests using System verilog and OVM. Prior Dfx experience is a Plus.
Additional Skills Desired (Nice to Have):
Should have worked on SOC validation before
ls (Must Have):
Should understand RTL verilog