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ASIC Design Engineer
- Location:
- Santa Clara, CA
- Area Code:
- 408
- Telecommute:
- no
- Travel Required:
- none
- Skills:
- RTL Synthesis, DFT, Static Timing Analysis, Floorplanning, Place-and-Route, Timing Closure
- Pay Rate:
- market
- Tax Term:
- CON_CORP CON_IND CON_W2 CON_HIRE_CORP CON_HIRE_IND CON_HIRE_W2
- Length:
- Date Posted:
- 4-25-2013
- Position ID:
- 950344
- Dice ID:
- 10231700
Repsonsible for RTL Synthesis, DFT insertion, Static Timing Analysis, Floorplanning and Timing Closure of blocks in advanced technology nodes.
You will be partially or fully responsible for all tasks from RTL-synthesis-->GDSII including physical verification (lvs/drc).
5+ years of experience in relevant field with BSEE/MSEE desired.
You will be partially or fully responsible for all tasks from RTL-synthesis-->GDSII including physical verification (lvs/drc).
5+ years of experience in relevant field with BSEE/MSEE desired.
Bharat Gohil
Sintegra Inc.
2328 Walsh Ave
Suite E
Santa Clara, CA 95051
Phone: (408) (408) 529-5433
Fax: (408) 521-2200
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