FPGA Designer

for The CEI Group in Berkeley, CA

Report
Skills:
BSCS/Math required and 15 years, or MSCS and 10 years of specific proven successful experience equivalent in the field of complex FPGA designs using Mathworks Simulink and Xilinx Tools Experienced pra 
Location:
Berkeley, CA
Area Code:
510 
Travel Req:
none 
Telecommute:
no 
Pay Rate:
$75-90/hr 
Tax Term:
CON_CORP CON_W2 
Length:
5-6 months 
Posted:
9-2-2014 
Position ID:
617758 
Dice ID:
compexpr 

OVERALL FUNCTION:

In collaboration with hardware and embedded software engineers, the FPGA Designer will lead development of Simulink models from scratch and from existing TI and Analog Devices DSP IP blocks.  The designer will instruct, guide, coach, train engineers on the best practices for Xilinx FPGA design and workflows between the Mathworks and Xilinx tools. The object is to support the engineering team to rapidly develop FPGA and DSP IP using Simulink for deployment onto Xilinx FPGAs.

 

ESSENTIAL RESPONSIBILITIES:

  • Coach Engineers in the fastest, best methods of Simulink Model generation from scratch and from existing C source code, TI and Analog Devices DSP IP.
  • Instruct, guide, coach, train and consult on best practices for Xilinx FPGA design and the use workflows between Mathworks Simulink and Xilinx ISC and Vivado products.
  • Support the engineering team to rapidly develop prototype models of IP from creation to validation.
  • Work one-on-one and in small teams to deploy projects, troubleshoot and de-bug designs after deployment.

 

REQUIRED SKILLS & EXPERIENCE:

  • BSCS/Math required and 15 years, or MSCS and 10 years of specific proven successful experience equivalent in the field of complex FPGA designs using Mathworks Simulink and Xilinx Tools
  • Experienced practitioner in HDL, Xilinx FPGA, SimuLink, Vivado, ISE…
  • Expert in Mathworks Simulink and Xilinx ISE and Vivado
  • Analog Devices SigmaStudio, proven development experience with
The CEI Group