JEDEC Jobs in San Jose, CA

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Sr Principal Hardware Developer

Oracle Corporation

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Santa Clara, California, USA

Full-time

Job Description About the role As a Sr Principal Hardware Developer, you will be(come) the technical lead on Memory in Oracle, supporting engineering, operations, OCI, Exadata and customers in the field along all aspect of product life cycle (Concept/NPI/Sustaining/EOL). You are the primary technical interface to internal engineering teams and memory suppliers as well as commodity and program teams within Oracle. You will provide input for memory RAS requirements to design teams and memory sup
Posted 54 days ago | Updated 2 hours ago

Lead Engineer - Hardware Test & Validation

Micron Technology, Inc.

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San Jose, California, USA

Full-time

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. We are core contributors in the test & validation of systems based on new memory technologies, ASICs, FPGAs, digital, mix-signal, analog circuitry, and power supplies PCBs and 3d models! You will
Posted 22 days ago | Updated 2 hours ago

RTL Design Engineer

Xoriant Corporation

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San Jose, California, USA

Contract

Title: RTL Engineer Location: San Jose, CA | San Diego, CA | Austin Texas Duration: 6+ months (Possible Extension-Long Term Project) Job Description As a senior RTL design engineer, you will work as part of a memory controller IP design team.You will be tasked with driving the RTL design, performance and power optimization of various sub-blocks of the dynamic memory controller.Solid engineer foundation and RTL design experience is desired for success.Key responsibilities include: Produce quality
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Posted 60+ days ago | Updated 9 hours ago

Memory Controller Designer/RTL Engineer at Austin TX/ San Jose CA/ San Diego CA

Mirafra Inc

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San Jose, California, USA

Full-time

Drive the timely development and debug of new features on timely development of custom memory controller. Working on SOC IP delivery with all sanity checks. Work on timing debug and closure. Working on LINT, CDC flows and analysis. Work on power artist flow and power analysis. Working on ECO flows. Work with the verification team to verify the functionality and correctness of the design. Collaborate with implementation to achieve your timing and area. Produce quality RTL on schedule meeting PPA