For over two decades, VHA has been a premier staffing provider of technology professionals in the Pacific Northwest. While it might seem unusual for a rapid-deploy, results-driven business like ours to take that responsibility personally, we do. Our President's work ethic not only serves as the foundation of our company, but drives the commitment to individual attention which infuses our culture. Our dedication is to the satisfaction and success of our clients and consultants. We're committed to providing outstanding service to a uniquely demanding industry in a straightforward, ethical, highly personal and always-responsive manner.

VanderHouwen & Associates, Inc., familiarly known to our clients and consultants as VHA, was established in Portland, Oregon, in 1987 by Kirby and Kathy VanderHouwen.

Position Information

VanderHouwen & Associates, Inc.
Beaverton, OR
Pay Rate:
Employment Terms:
Job Length:
Full time
Required Skills:
SoC/ASIC Matlab
Position ID:

Contact Information

6342 SW Macadam Ave.
Portland, OR 97239
(503) 299-6811

Job Description

  • Job Description

Sr. Systems Engineer (SoC/ASIC Matlab)

Responsible to develop high end SOC architectural solutions according to customer specifications, finding optimum tradeoffs between system performance, power dissipation and cost.
Develop, run and maintain system Matlab models for SoC across various usage modes.
Explore different modulation schemes and usage scenarios to ensure compliance of SoC system model with customer requirements.
Design high performance, power efficient z-domain filters, optimize coefficients, and work with digital team to ensure proper implementation. Simulate entire DSP chain, in the custom digital flow, using make-files, octave, Verilog.
Build-up and own chip top simulations that verify wireless and wire-line modulation modes are implemented correctly.

Ph.D. in Communications is required.
5+ years of experience modeling communication systems with Matlab is required.
Good knowledge of communication systems/standards and their application to different wireless and wire-line applications. Understand key system design trade-offs
Excellent skill with digital RTL development using Verilog.
Working experience with mixed SoC/ASIC modeling languages like System Verilog, Verilog-AMS, Simulink
Experience with Unix/Linux scripting languages such as unix-shell, Python, PERL, TCL, etc.
Self-driven, able to work independently while coordinating with IC designers