You will be contributing to the verification effort of a complex chip, sub-system and/or blocks. You will define chip level verification strategies, test planning, and develop all necessary tools and scripts to enable system-level testing in an automated fashion. You will work with the block/core teams to develop re-use verification. You will verify a core or subsystem at the system level for interactions, connectivity, bus certification for robust verification.
- 3+ years of experience in ASIC/SoC Verification
- Strong knowledge in Object Oriented programming, data structures, and algorithms
- Strong knowledge of HVLs(VERA/e/SystemVerilog), HDLs(Verilog/VHDL), C/C++
- Must have hands-on experience and strong knowledge on HVL methodology (UVM, OVM, VMM, RVM), testbench automation, industry standard bug tracking, and regression mechanisms.
- In-depth knowledge in SoC architecture, including CPUs (preferably ARM), memory subsystems and controllers (PCDDRx), peripherals (PCIe, SATA, Ethernet) , multi-domain clocking, and bus & interconnect structures (preferably as AHB and AXI) - Must have excellent system debug skills
- Excellent oral and written communication skills
- Ability to work in a team environment
Important required skills:
-Experience with TCP offload and DMA.
-Extensive UVM/System verilog skills, as well as exposure to DDR, I2C, AMBA, and PCIe testing.
-Exposure to different kinds of IP blocks
-Experience with SoC verification for server chips, including test planning, test creation (in ASM), and functional coverage generation
Candidates must have US citizenship or current authorization to work in the US that meets ITAR regulations. Xpeerant cannot provide support for Visa applications. Relocation reimbursement is not offered.