Verification Engineer 100% Remote

Verification Engineer 100% Remote

We are seeking a highly skilled Formal Verification Engineer to join our verification team and help drive high-quality sign-off for complex hardware designs. The ideal candidate has strong experience with formal verification tools (VC Formal or JasperGold), deep understanding of SystemVerilog Assertions (SVA), and the ability to define and execute verification strategies for robust verification closure.

• Define comprehensive formal verification plans, strategies, and methodologies to achieve high-quality verification sign-off.
• Review and contribute to RTL design architecture and specifications to ensure formal verifiability.
• Develop and prove SystemVerilog Assertions (SVA) to validate design intent and corner cases.
• Use formal verification techniques-including model checking, logical equivalence checking, and theorem proving-to prove functional correctness of design features.
• Collaborate with simulation teams to provide formal sign-off and ensure full verification closure for IP blocks and subsystems.
• Build, enhance, and maintain regression environments, infrastructure, and tooling for formal verification workflows.
• Analyze verification results, root-cause failures, and provide actionable insights to design and architecture teams.
• Support and improve integrated formal + simulation-based verification methodologies across the organization.

Skills:

• SystemVerilog
• SVA
• RTL Design
• Formal sign-off
• Verification Methodologies
• Debugging