Overview
On Site
Depends on Experience
Accepts corp to corp applications
Contract - Independent
Contract - W2
Contract - 2 Year(s)
No Travel Required
Able to Provide Sponsorship
Skills
FPGA verification.
UVM
Python
Perl
Verilog
QuestaSim
Synopsys VCS
Job Details
Job Description,
Strong understanding of FPGA design principles and architectures.
Proficiency in System Verilog and UVM verification methodology.
Experience with industry-standard verification tools (e.g., QuestaSim, Synopsys VCS).
Knowledge of code coverage and functional coverage analysis.
Excellent debugging and problem-solving skills.
Strong communication and collaboration skills.
Requirements
Bachelor s or master s degree in electrical engineering, Computer Engineering, or a related field.
Experience in FPGA verification.
Experience with scripting languages (e.g., Python, Perl).
Familiarity with hardware description languages (e.g., VHDL, Verilog).
Proficiency in System Verilog and UVM verification methodology.
Experience with industry-standard verification tools (e.g., QuestaSim, Synopsys VCS).
Knowledge of code coverage and functional coverage analysis.
Excellent debugging and problem-solving skills.
Strong communication and collaboration skills.
Requirements
Bachelor s or master s degree in electrical engineering, Computer Engineering, or a related field.
Experience in FPGA verification.
Experience with scripting languages (e.g., Python, Perl).
Familiarity with hardware description languages (e.g., VHDL, Verilog).
Must Have Skills FPGA Verification Engineer
Skill 1 8 + Years of in FPGA
Skill 2 5 +Years of Exp in UVM
Skill 2 5 +Years of Exp in System Verilog
Skill 1 8 + Years of in FPGA
Skill 2 5 +Years of Exp in UVM
Skill 2 5 +Years of Exp in System Verilog
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