Verification Engineer - Remote

Overview

Remote
$90.54 - $95.54
Contract - W2
Contract - 6 Month(s)

Skills

UVM
UVM design verification
UVM verification
UVM environment
AISC
SOC
AISC verification
SOC verification
DV tools
DV methodologies
CPU
I/O
Cadence
Synopsys Verification tools
Synopsys
Verdi
System Verilog
IP
I/O SOC
UVM test bench development
design verification
test plan
test verification

Job Details

Title: Verification Engineer - Remote


Mandatory skills:


UVM, UVM design verification,
UVM verification, UVM environment,
AISC, SOC,
AISC verification, SOC verification,
DV tools, DV methodologies,
CPU, I/O, Cadence, Synopsys Verification tools, Synopsys, Verdi,
System Verilog, IP, I/O SOC, UVM test bench development,
design verification, test plan, test verification


Description:


JOB DUTIES:
Participate in the functional verification of a block(s) of complex ASICs and/or IP cores for a combined CPU/GPU development effort. Be part of a team of design and verification engineers, working closely with other team members to understand and verify the functionality of a given design element within the context of the block, chip and overall system. Be responsible for carefully documenting and executing test plan(s) consisting of directed and constrained-random tests to be run during simulation. Be expected to adopt the evolving verification methodologies used in the industry to functionally verify increasingly more complex SoC designs within aggressive, market-driven schedules, and work within the existing verification infrastructure on currently active projects. Be familiar with hardware modeling and/or assertion-based verification methods.

EXPERIENCE AND EDUCATION:
7 or more years of proven verification experience on large ASIC development projects or software/firmware experience in a hardware development setting
Strong background in C/C++ development in a Linux Environment
Strong debug skills and experience with debug tools such as Gdb, Valgrind
Proficient in Object Oriented programming, STL, computer architecture and data structures
Knowledge of Perl and Makefiles
Experience in Verilog/SystemVerilog/SystemC,
Experience in C/Verilog environment using DPI/PLI

UVM - System Verilog
5+ years work experience
Worked on complex SoC
Strong computer architecture knowledge
Prefer DRAM / Memory Controller experience
B.S. in EE or Computing preferred

Preferred:
Strong analytical skills and attention to detail; Excellent written and communication skills


VIVA USA is an equal opportunity employer and is committed to maintaining a professional working environment that is free from discrimination and unlawful harassment. The Management, contractors, and staff of VIVA USA shall respect others without regard to race, sex, religion, age, color, creed, national or ethnic origin, physical, mental or sensory disability, marital status, sexual orientation, or status as a Vietnam-era, recently separated veteran, Active war time or campaign badge veteran, Armed forces service medal veteran, or disabled veteran. Please contact us at for any complaints, comments and suggestions.


Contact Details :

VIVA USA INC.
3601 Algonquin Road, Suite 425
Rolling Meadows, IL 60008

Employers have access to artificial intelligence language tools (“AI”) that help generate and enhance job descriptions and AI may have been used to create this description. The position description has been reviewed for accuracy and Dice believes it to correctly reflect the job opportunity.

About VIVA USA INC