RF - ASIC Design Engineer

Full Time



    Job Description

    Location: San Diego, CA
    Salary: $170,000.00 USD Annually - $220,000.00 USD Annually
    Description: The Judge Group has partnered with a cutting-edge semiconductor system provider in the architecture evolution, design, and development of 5G and beyond, as well as smartphone technology research.
    Our client is seeking a RF - ASIC Design Engineer, position is hybrid and reports onsite in San Diego, CA or Palo Alto, CA. This is a Direct Hire Opportunity.

    *** For immediate consideration, please email your resume to: ***

    In a multi-site project team, you are working on the design and implementation of the custom ASIC design and integration of such blocks into high performance RF radios for cellular (4G/5G) and Connectivity (WiFi/Bluetooth/GNSS) as part of a multi-site project team.


    • Top/Block level RTL (Verilog or System Verilog) design, integration and test.
    • Work with RF/Analog IC design teams to implement calibration algorithms and control functions (in Verilog) for analog circuits such as ADC & DAC, Phase Lock Loops (PLLs).
    • Design and implement Digital Signal Processing functions for digital receivers and transmitters such as FIR filters and Gain Control.
    • Design and implement microprocessors/memories/peripheral control.
    • Work with Test Teams to verify digital and analog radio functionality.
    • Develop FPGA Designs (Altera/Xilinx) for radio test & prototype platforms.
    • Optimize ASIC for power, performance, area and timing.
    • Participate in Physical Design of ASICs: Synthesize, Scan Insertion, ATPG, Floor Planning, Place and Route, Timing Closure, Formal Verification, Static Timing Analysis, Back Annotation Sims.


    • BSEE is required. MSEE/Ph.D. in electrical engineering with desired experience in digital ASIC / FPGA design is preferred.
    • 5 or more years of experience in ASIC/FPGA design, verification or related work knowledge.
    • RTL design with Verilog, System Verilog or VHDL.
    • FPGA design using Quartus or Vivado.
    • Familiarity with front-end, middle-end, and back-end ASIC design tools (Cadence/Synopsys). Familiarity with lab equipment (Logic Analyzers, Oscilloscopes, Spectrum Analyzers).
    • Experience with scripting tools such as Perl, Matlab. Knowledge of radio transceivers, digital signal processing, and microprocessors
    • Proven track record of completing complex designs on time.


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