Position: Sr DFT engineer
Full Time opportunity in Campbell, CA
Seeking a seasoned SrDFT engineer with a minimum of 15+ year of experience to join our ASIC team. Person should have prior in defining the DFT Architecture and execute on the DFT implementation plan. This means defining the methodology, setting up the environment and driving the Synthesis/Formal Implementation flows in a Hierarchical DFT environment. Comprehensive understanding of the issues faced between the RTL, DFT and the Physical design Teams. Good understanding of clocking structures and tradeoffs between Power, area and timing.
- Expertise is SDC and Verilog is mandatory.
- Leading ASIC infrastructure, defining methodology and driving the DFT flows.
- Expertise in ACJTAG/BSD/1500 wrappers
- Expertise in Scan/ On chip Clocking/@speed Test (TDF) /Path Delay
- Prior experience with Serializers and In system Sc an
- Strong experience in ECO methodology.
- Driving Backend Test generation and wafer/ATE Test with external Vendors.
- Work with hardware Team to promote SDC’s in a multi-level Physical hierarchical design.( Hierarchical DFT/Test).
- Work with Physical design Time to refine constraints.
- Work with Timing team to consolidate Timing Modes. STA experience preferred.
- PERL /TCL programming ability required.
- Prior tapeout experience required in a 16nm environment or smaller.
- Strong communication and presentation skills.
- BSEE/MSEE is required.