FPGA Verification Engineer

  • Santa Clara, CA
  • Posted 19 hours ago | Updated 19 hours ago

Overview

On Site
Depends on Experience
Accepts corp to corp applications
Contract - W2
Contract - 12 Month(s)

Skills

FPGA
UVM
System Verlilog

Job Details

FPGA Verification Engineer

Santa Clara, CA

Must Have Skills

8 + Years of in FPGA

5 +Years of Exp in UVM

5 +Years of Exp in System Verlilog

Job Description:

We are seeking a highly motivated and skilled FPGA Verification Engineer to join our dynamic team. In this role, you will be responsible for the verification of complex FPGA designs, ensuring their functionality, performance, and reliability. You will work closely with design engineers to develop and execute verification plans, identify and debug issues, and contribute to the overall quality of our products.

Skills Required:

Strong understanding of FPGA design principles and architectures.

Proficiency in SystemVerilog and UVM verification methodology.

Experience with industry-standard verification tools (e.g., QuestaSim, Synopsys VCS).

Knowledge of code coverage and functional coverage analysis.

Excellent debugging and problem-solving skills.

Strong communication and collaboration skills.

Requirements:

Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field.

3+ years of experience in FPGA verification.

Experience with scripting languages (e.g., Python, Perl).

Familiarity with hardware description languages (e.g., VHDL, Verilog).

Employers have access to artificial intelligence language tools (“AI”) that help generate and enhance job descriptions and AI may have been used to create this description. The position description has been reviewed for accuracy and Dice believes it to correctly reflect the job opportunity.