RTL Design Engineer

Depends on Experience

Contract: Corp-To-Corp, Independent, W2, 12 Month(s)


    RTLFPGAASICDesignPCIEAPB protocols

    Job Description

    Job Title: RTL design engineer Location: Bay Area, CA

    Roles and Responsibilities

    • Collaboration with offshore team.
    • IC role and offshore task coordination
    • Must have 10+ yr experience with ASIC design activities – Verilog RTL, testcase debug, netlist checks, CDC checks, coverage analysis, timing closure, x-prop/gate level simulations.

    Nice to Have:

    • Domain knowledge in PCIE/CXL, DDR, AMBA AXI/APB protocols.
      Please note: We strongly prefer the ASIC experience. If FPGA-only experience, then domain knowledge is must.