ASIC/FPGA Verification Engineer

$100 - $115

Contract: W2, 6 Month(s)

  • Work from home
  • No Travel Required


  • asic verification
  • fpga verification
  • verilog
  • uvm

Job Description

Job Title: ASIC/FPGA Verification Engineer

Location: San Jose, CA

Duration: 6+ months (Possible Extension-Long Term Project)

Rate: $115/hr on w2


  • Participate in internal design and code reviews
  • Setup complete verification environment
  • Develop test plans and creating tests
  • Perform code and functional coverage and analyze coverage reports
  • Setup and run gate level simulations with SDF


  • Master's degree
  • 7 years of ASIC/FPGA verification experience using one of the common verification methodology (i.e. systemVerilog, UVM)
  • Hand-on experience with code and functional coverage
  • Hand-on experience with gate level simulation
  • Familiar with high speed interface protocols is a plus
  • Good oral and written communication skill