Overview
On Site
$140,000 - $180,000
Full Time
Skills
ASIC
UVM
Job Details
Key responsibilities:
- Review and as needed develop comprehensive test plan strategies and ability to prioritize features based on architecture, specification, design knowledge, and feedback
- Strong skills in creating and maintaining UVM-based verification environments, including writing testbenches, sequences and integrating reusable component architectures
- Implement functional coverage models and ensure coverage closure for blocks and subsystems
- Ability to debug complex design and verification issues using industry best practices and advanced tools
- Assist with assertion-based verification, code coverage analysis, and regression management
- Write and maintain verification scripts to streamline verification workflows and regression monitoring
- Monitor regressions, triage failures, and drive resolution by collaborating with design and verification teams
- Work closely with cross-functional teams, including architects, designers, software/firmware engineers, to ensure seamless integration and verification
- Strong collaboration skills and initiative to reach out to FTE engineers on the verification of IP, subsystems, or SoCs during verification planning and debug of existing blocks and subsystems
- Ability to mentor and guide junior engineers when needed
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