- Design for Test
Title: Design for Test (DFT) Engineer
Location: San Jose, CA
Duration: 6+ months (Possible Extension-Long Term Project)
Rate: $100/hr on w2
- Design for Test (DFT) Engineer 5 years’ experience with the following:
- ATPG (stuck, transition delay, bridge) with Synopsys Tetramax/Mentor TestKompress
- ATPG pattern generation, coverage analysis and ATPG simulation.
- Ability to debug ATPG simulation failures is a plus.
- DFT insertion using DFT Compiler
- Good TCL and PERL scripting skills
- MBIST insertion using Mentor Tessent, including memory repair.
- Ability to run and debug - MBIST simulations.