FPGA/ASIC Design Engineer

Job Title: FPGA/ASIC Design Engineer

Location: 2235 Monroe St, Reston, VA
Schedule: 9/80 Work Schedule 8:00 AM Start
Category: Technical / Professional
Clearance Required: Active SECRET Clearance
Level: Mid Senior
Employment Type: Full-time / Contract

Job Overview:

L3Harris Technologies is seeking an experienced FPGA/ASIC Design Engineer to join our high-performance engineering team focused on developing secure, high-speed crypto communication products for national security missions. The successful candidate will be part of a dynamic ASIC/FPGA team responsible for architecting, implementing, verifying, and delivering FPGA/ASIC-based communication solutions leveraging Xilinx Zynq/MPSOC and high-speed networking protocols.

This position offers the opportunity to work on state-of-the-art EDA tools and cutting-edge hardware design methodologies within a mission-critical defense environment.

Key Responsibilities:

• Derive engineering specifications from system-level requirements and develop detailed hardware architecture.
• Design and implement RTL (VHDL/Verilog) or HLS (C++ to RTL) logic for high-performance communication systems.
• Execute RTL quality checks including CDC, RDC, Lint, and Formal Verification.
• Develop and execute test plans for FPGA/ASIC modules and systems.
• Perform module-level verification, synthesis, and static timing analysis (STA).
• Conduct lab debugging and software-driven validation on Linux-based SoC evaluation boards.
• Support silicon/FPGA bring-up, characterization, production ramp, and documentation deliverables.
• Collaborate cross-functionally with software, hardware, and systems teams for end-to-end solution delivery.

Required Skills & Experience:

• Bachelor s degree in Electrical Engineering or equivalent discipline and 4+ years of relevant experience (or Master s + 2 years).
• Active SECRET clearance is mandatory.
• Minimum 5+ years of experience in VHDL design and FPGA development using Xilinx Vivado.
• Hands-on experience in full design lifecycle: architecture, RTL coding, verification, synthesis, STA, and FPGA bring-up.
• Experience with Ethernet, TCP/IP, AXI and other high-speed networking protocols.
• Strong analytical and debug skills at both logic and board levels.
• Excellent communication and documentation skills.

Preferred / Plus Skills:

• Experience with High-Level Synthesis (HLS) using Vivado or Mentor Catapult (Calypto).
• Knowledge of SystemVerilog Assertions (SVA) and Universal Verification Methodology (UVM).
• Experience in C++ (OOP) and embedded software integration (SDKs, BSPs, PetaLinux OS).
• Familiarity with Mentor EDA tools: Questa, CDC/RDC, Lint, and VIPs.
• Background in Aerospace/Defense or high-security communication systems.
• Prior experience in project leadership or earned value management (EVM) is a plus.

Tools & Technologies:

• EDA Tools: Synopsys DC/Primetime/Synplify, Xilinx/Intel/Microchip EDA, Mentor Questa, VIPs, Catapult (HLS)
• Protocols: Ethernet, TCP/IP, AXI, PCIe
• Languages: VHDL, SystemVerilog, C++, HLS (C++ to RTL)
• Platforms: Xilinx Zynq / MPSoC, Linux-based SoC Evaluation Boards

Submission Requirements:

Please include the following details with your submission:

• Legal Full Name (no nicknames)
• Last 4 digits of SSN
• Date of Birth (MM/DD)
• Email Address