Overview
Skills
Job Details
Job Title: Verification Lead UVM / System Verilog / RTL Verification
Location: 100% Onsite Austin, TX
12+ Months Contract
Top Must-Have Skills:
- UVM
- System Verilog
- RTL Verification
Role Overview:
We are seeking a seasoned Verification Lead with expertise or strong interest in IO/PHY verification. The ideal candidate will have a proven track record in IP verification, UVM, and SystemVerilog, with the ability to lead Design Verification (DV) teams and collaborate with world-class design and engineering professionals.
This senior role provides an opportunity to take ownership of verification projects, define verification strategies, and mentor junior engineers to achieve technical excellence.
Key Responsibilities:
- Define comprehensive verification plans and provide technical leadership to execution teams.
- Review AMS, Firmware, and design specifications to create an effective DV strategy.
- Develop UVM/SystemVerilog based testbenches and test cases.
- Drive bug-free design sign-off through rigorous functional and formal verification.
- Lead Formal Verification activities.
- Collaborate with Post-Si teams for debugging and resolution of performance, power, and functional issues.
Preferred Experience:
- Strong knowledge of IO/PHY verification.
- Hands-on experience in Formal Verification methodologies.
- Exposure to Firmware and hardware/software integration.
- Excellent communication, leadership, and presentation skills.
- Proven ability to collaborate across cross-functional teams and geographies.
Education:
Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field