- Cadence Virtuoso
- digital circuits
- layout design
The candidate should be able work independently on block level and IP level Analog layout design, coordinating with the circuit designer and the rest of the layout team. The candidate will need to be able to work with both design engineers and mask design engineers in remote locations, and thus the ability to plan and efficiently use email and Webex to review critical aspects of the layout work is essential to this role.
The candidate should have experience with the layout of high-frequency analog and high-speed custom digital circuits in which parasitic minimization is critical.
The candidate should be able to understand how to implement design requests including pwr/gnd nets, critical device matching, and sensitive signal routing. They should be able to recognize how decisions at their level of integration affects the design hierarchy above and below their level. They should have a good understanding of ESD concepts including how to best use guard rings for design isolation.
The candidate should be comfortable asking questions of the rest of the layout team, the candidate will be expected to share items that they feel may help others in the layout team.
The candidate should have experience in using Cadence Virtuoso and also the calibre LVS and DRC checking tools. Some expertise in basic Unix scripting is a plus.
Candidate should have minimum 10-15+ years of hands-on experience in Analog or RF layout. Experience with analog modules such as SerDes, ADCs/DACs, and PLLs is a plus. Candidate should have good understanding of analog layout concepts for deep sub-micron processes and knowledge of fabrication process, and experience in layout in FinFet technologies is required. Preference will be given for candidates with experience in 7nm and 5nm process nodes.
Education should include a Bachelor of Science degree.