Senior Design Verification Engineer

Role summary

Seeking a Senior Design Verification Engineer with 8+ years of experience in IP and subsystem‑level verification using SystemVerilog and UVM. The engineer will own verification of complex digital IPs/sub‑systems, drive coverage closure, and collaborate closely with RTL, architecture, and validation teams to deliver high‑quality silicon.

 Key responsibilities

- Own verification of one or more IPs or subsystems (e.g., interconnect, memory, I/O, compute blocks) from testplan to coverage closure.
- Develop and maintain UVM‑based verification environments: agents, drivers, monitors, scoreboards, checkers, and sequence libraries at IP and SS level.
- Create verification plans from architecture/micro‑architecture specifications, define coverage metrics (functional, code, assertions), and track progress to sign‑off.
- Implement constrained‑random and directed tests, analyze regressions, triage and root‑cause failures, and work with RTL designers for timely bug resolution.
- Integrate and verify 3rd‑party IP/VIP and transactors; support subsystem integration and bring‑up in simulation/emulation as needed.
- Write and review SVAs, drive assertion‑based and coverage‑driven verification methodology improvements.
- Automate flows for regressions, result analysis, and coverage reporting using scripting (e.g., Python/Perl/Tcl, Makefiles, CI).

 Required qualifications

• BS/MS in EE/CE/CS or equivalent.  

- 8+ years of hands‑on ASIC/SoC design verification experience at IP and/or subsystem level. expertise in SystemVerilog and UVM, with a track record of building reusable, scalable testbenches and components.

- Solid experience with coverage‑driven verification, including definition and closure of functional/code coverage.

- Proficiency with industry‑standard simulators and debug tools (VCS, Questa, Xcelium, Verdi or similar).

- Good understanding of common on‑chip protocols (e.g., AMBA AXI/AHB/APB) and typical IP types such as memory, interconnect, or I/O subsystems.

- Strong debug skills, ability to analyze waveforms, logs, and coverage to quickly isolate issues.

- Solid scripting skills (Python/Perl/Shell/Tcl) for automation and productivity.

 Preferred qualifications

-Experience with SoC‑level or SS‑level verification, including integration of multiple IPs and system scenarios. 

- Exposure to high‑speed or complex protocols such as PCIe, CXL, Ethernet, or similar. 
- Experience with low‑power/UPF verification, gate‑level sims, emulation, or FPGA prototyping. 
- Familiarity with CPU/accelerator verification, cache/memory subsystems, or coherence is a plus.