Overview
On Site
$60 - $70
Contract - W2
Contract - 12 Month(s)
Skills
Certified Interconnect Designer (CID
CID+)
PCB LayOut
designing complex
impedance controlled multi-layer (>20)
PTH and HDI PCBs with high pin count devices (>8K)
high-speed interfaces (PCIe Gen5/6 and LPDDR5/6)
differential pairs
high-current power planes
SOC
FPGA
Job Details
- Highly experienced with the layout of PCB platforms for embedded compute.
- Experience of designing complex, impedance controlled multi-layer (>20), PTH and HDI PCBs with high pin count devices (>8K), high-speed interfaces (PCIe Gen5/6 and LPDDR5/6), differential pairs, high-current power planes.
- Experience of working alongside a chip packaging team.
- Able to influence and advise on pinout and routing topologies of SoC's or complex FPGA devices, cost optimisation, routing feasibility and layer trade-off analysis.
- Detailed knowledge of escape routing of high density SoC's, FPGAs, able to provide estimates of the IO count that can be routed with a particular stack-up and rule set.
- Appreciation of Signal Integrity and Power Integrity as applicable to routing strategies.
- Extensive knowledge PCB fabrication of complex multi-layer stack ups (PTH & HDI), IPC standards and substrate materials, via structures and design rules.
- Proficient in the use of EDA Tools, specifically Cadence OrCAD CIS / Allegro PCB suite.
- Ability to collaborate with PCB fabricators for DFM/DFT and automated assembly.
- Ensure designs are aligned with leading edge suppliers and best practise.
- Good interpersonal and communication skills.
- Certified Interconnect Designer (CID, CID+)
- Experience with version control systems (e.g. SVN)
- Experience of automating: decoupling capacitor optimisation, IC placement optimisation, drawing templates etc.
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