Responsible for Design for Test (DFT) of high performance (>2 GHz) CPU subsystems using latest DFT methodologies/techniques.
Define and implement DFT architecture to enable all the test coverage goals are met. Responsible for generating test pattern and simulating them in Gate Level simulations.
Responsible for generating and verified MBIST controller.
Generate and debug failing patterns on Silicon.
4+ Years of hands on experience in Design for Test (DFT) of high speed (>2.5GHz) Complex IP, CPU Subsystems and/or SoC.
Experienced in latest DFT methodologies for High Speed (>3 GHz) designs: Scan insertion, Scan compression, ATPG pattern generation, At-Speed testing.
Experienced in MBIST, able to generate MBIST controller based on spec and verify MBIST patterns.
Experienced in defining and deploying DFT architecture for complex designs preferably CPU subsytems or SoCs to meet the test coverage goals
Expert at using industry standard DFT tools, preferably Synopys DFT compiler and Tetramax, Tessent-MBIST.
Proven Ability to simulate and debug DFT patterns using Gate Level Simulations (GLS)
Experience in pattern porting from IP to SOC level; running and debugging DFT patterns during Silicon bring-up
Excellent communication skills and ability to communicate and work with other world-wide sites
Experienced in pattern level.
Proven ability to develop and deploy new DFT methodologies.
Strong scripting skills using Perl, Tcl, or Python
Knowledge of JTAG