Title: Verification Engineer
ASIC design verification, FPGA design verification,
SystemC, C++, C programming,
interface protocol, constraint, test suites, feature integration, RTL blocks, simulation debug,
ASIC design flow,
Verilog RTL design,
CAD tools, coverage reporting, profiling
Member of Technical Staff Design Verification Engineer
We focus on video codec IP development for the client SOCs with leading ASIC technology.
We are looking for a self-motivated, experienced (MTS level) verification engineer in the Austin, TX, area to complement our team to develop world class video solutions verified to the highest standards.
You are expected to actively collaborate with various team members to understand design requirements, drive block-level verification, support IP level integration and verification, and pursue functional and code coverage closure linked back to requirements throughout the design cycle. Solid technical skills, a self-driven attitude, and excellent communication skills especially remotely are key factors to be successful in our organization.
Draft block-level verification plan with functional coverage specification.
Construct block-level testbenches using UVM.
Devise and implement block-level tests, and manage regression suites with performance and scalability considerations
Triage test run failures and provide debug support to design engineers to isolate the causes.
Actively drive simulation throughput profiling and use state-of-the-art practices to help optimize regression turnaround times.
Own verification of the design across multiple abstractions and views, including C-model simulation, RTL simulation and formal verification.
Ensure the design can meet performance targets with accurate modeling of interface protocol behavior in the block-level testbenches in aligned with IP level behavior with top-down constraints.
Conduct coverage analysis, profiling, and reporting, and augment test suites towards coverage improvements and sign-off.
Support IP-level feature integration and bring-up of RTL blocks and assist in IP-level simulation debug.
Minimum 7 years of solid ASIC/FPGA design verification experience.
Rich knowledge of ASIC design flow from specification to implementation and verification.
Well-versed in UVM.
Strong in SystemC, C++/C programming.
Solid knowledge of Verilog RTL design.
Experience with HLS flow in complex design implementation and verification is a definite asset
Familiar with simulation CAD tools including coverage reporting and profiling.
Handy in Linux scripting languages such as Perl, Python, Ruby and/or shell languages.
Solid problem-solving skills.
Prior team or technical leadership, or mentorship, are great value-added assets
Excellent team player and communicator
Basic video codec knowledge is a definite plus.
Minimum Bachelor of Science Degree in Electrical Engineering, Computer Science, or Computer Engineering.
VIVA USA is an equal opportunity employer and is committed to maintaining a professional working environment that is free from discrimination and unlawful harassment. The Management, contractors, and staff of VIVA USA shall respect others without regard to race, sex, religion, age, color, creed, national or ethnic origin, physical, mental or sensory disability, marital status, sexual orientation, or status as a Vietnam-era, recently separated veteran, Active war time or campaign badge veteran, Armed forces service medal veteran, or disabled veteran. Please contact us at for any complaints, comments and suggestions.
Contact Details :
VIVA USA INC.
3601 Algonquin Road, Suite 425
Rolling Meadows, IL 60008