RTL Design Engineer

RTL Design
Full Time
Depends On Experience
Travel not required

Job Description

Job Description:


  • Develop RTL for designs which encompass both control logic and numerical computation
  • Perform initial verification of the design
  • Develop simulation models in SystemVerilog for complex RTL blocks


Qualifications and requirements:

  • BS, MS, PhD in electrical or computer engineering or related field and at least 7 years of related experience
  • Extensive experience with finite state machine design
  • Must have some DSP experience or be very familiar with 2s compliment and have worked in a signal processing environment
  • Experience with RTL designs in Verilog
  • Experience building simulation models in SystemVerilog
  • Experience with verification testbenches in Verilog and SystemVerilog
  • Must have excellent communications skills and a proven track record of being a self-starter

Posted By

Mike Buckley

2200 Laurelwood Road Santa Clara, CA, 95054

Dice Id : 10121377
Position Id : 132085
Originally Posted : 7 years ago
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