ASIC Design Verification Engineer

asic, ovm, soc, uvm
Full Time, Contract Corp-To-Corp, Contract Independent, Contract W2, 1 year
Work from home available

Job Description

ASIC Design Verification Staff Engineer

Phoenix or Bay Area

Responsibilities:

Must have 5+ years of experience

Testbench development - System Verilog UVM and C tests

Integration/development of C tests/APIs and SW build flow

Integration/development of UVM mailboxes and HW/SW communication components

Integration of lower level UVM testbenches

Test plan development

Power Aware testbench development and simulations

Seamless porting between simulation/emulation/prototyping platforms

Regression setup and debug for RTL/Gate Level Netlist/UPF PA sim/Emulation/Proto

Coverage collection and closure

Working with cross functional teams (DV/Arch/Design/FW) to identify coverage scope

Dice Id : 90995872
Position Id : 2021-33
Originally Posted : 8 months ago
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