Senior FPGA Design Engineer

timing closure, FPGA, RTL coding, test bench development, hardware verification, troubleshooting, VHDL, Verilog, DSP, MIMO, wireless systems, multiple clock-domain, Xilinx FPGAs, Xilinx SoCs, Vivado IDE, Matlab, C, C++
Full Time
Depends on Experience
Travel not required

Job Description

Silvus Technologies is seeking FPGA Design Engineers to participate in the design and development of our StreamCaster line of MIMO mesh networking products and participate in advanced wireless systems R&D.

The Company

Silvus Technologies is a fast-growing, wireless engineering company located in the heart of West Los Angeles. Founded in 2004, Silvus has developed and produced multiple generations of its StreamCaster line of MIMO radios the most technologically advanced Mobile Ad-Hoc Networking (MANET) solution available. In addition to our successful MANET product line, Silvus also conducts ground breaking research in the area of wireless data communications and has executed on over $54M in R&D contracts for the US government and commercial entities. Our technical team members possess very strong interdisciplinary capabilities and have provided innovative solutions to a broad range of important challenges for customers in military communications, law enforcement, public safety, commercial broadcasting, unmanned/drone systems and more.

Technical Responsibilities

Our FPGA designers actively participate in all aspects of the development process from concept to field deployment:

  • FPGA design architecture definition
  • Fixed point system simulations
  • RTL coding and test bench development
  • FPGA design synthesis and timing closure
  • Hardware verification and troubleshooting


  • Must be a U.S. person (permanent resident or citizen) due to clients under government contract
  • MSEE required, Ph.D in Electrical Engineering a plus
  • 4+ years of FPGA design experience required
  • Proficient in VHDL (preferred) or Verilog (2+ years preferred)
  • Experience with Digital Signal Processing (DSP), MIMO, wireless systems is a plus
  • Experience with multiple clock-domain, high-speed, high-utilization FPGA designs
  • Experience with Xilinx FPGAs, SoCs and the Vivado IDE
  • Experience with Matlab/C/C++ is a plus (2+ years preferred)
  • Ability to pass background check
Dice Id : 10284629
Position Id : 5968989
Originally Posted : 3 years ago
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