Design Verification Engineer

UVM, Verification
Contract W2, 6 Months
$70 - $80
Travel not required

Job Description

Job Title: Design Verification Engineer

Location: San Jose, CA

Duration: 6+ months

(5+ years of experience is mandatory)

Share your resume if you can work on w2,



  • Triage regression failures and make testbench updates
  • Debug functional errors in RTL model using simulation and debug tools
  • Maintain efficient and clean regression status
  • Develop Scalable SystemVerilog/UVM testbenches for unit level and/or Cluster level verification
  • Review Architecture and Micro-Architecture specifications
  • Closely work with Architects and RTL designers
  • Define, maintain and execute unit level and/or Cluster level verification testplans
  • Generate and run Testcases on logic simulation models
  • Code Functional coverage models and System Verilog assertions
  • Drive Functional Coverage and Code coverage to closure


  • 5 + year s industry experience in a design verification role
  • Proficient in System Verilog/UVM/OVM, OOP/C++
  • Knowledge of GPU, experience with Shader, Texture, or Memory System a plus
  • Experience with code coverage and functional coverage driven verification methodology
  • Experience in creating, running and debugging of SystemVerilog/UVM constraint-random Testbench
  • Excellent working knowledge of scripting languages such as Python or Perl


Thanks & Regards,

Lekha Dhole

Desk : 475-209-7073

Xoriant is an equal opportunity employer. No person shall be excluded from consideration for employment because of race, ethnicity, religion, caste, gender, gender identity, sexual orientation, marital status, national origin, age, disability or veteran status. 

Dice Id : xorca001
Position Id : 6355854
Originally Posted : 11 months ago
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