Physical Design Engineer

physical design, soc design, asic design, cpu design, gpu design, pnr, p&r, place and route, place & route, finfet, synthesis, floorplan, block, sta, cts
Contract W2, 6 Months
$80 - $85
Travel not required

Job Description

Job Title: Physical Design Engineer

Location: San Jose, California

Duration: 6+ Months (possible extension) (remote work allowed during covid)

Responsibilities:

  • Hands-on responsibility from synthesis to place and route of a System-IP block through signoff flows including timing and physical verification ·
  • Synthesis, Floor plan, Place & Route in chip-level and hierarchical physical implementation environment ·
  • Running MBIST and DFT insertion into block, understanding impact of MBIST/Scan and debug logic is desirable
  • Interact with RTL counterpart to resolve design issues pertaining to block closure ·
  • Optimize GPU block to meet aggressive power/performance/area targets Requirements

Minimum requirements:

  • Solid understanding and working knowledge of the SOC/ASIC/GPU/CPU design flow with some experience in taping out designs
  • Hands-on experience with synthesis, block and full chip implementation with the latest industry P&R/STA flows and tools
  • Experience in block level floor-planning, implementing power grid and power/area/performance optimization
  • Strong scripting/programming skills in Tcl, Perl, Shell, and/or Python
  • Solid understanding of Electrical Engineering fundamentals, analytical aptitude and excellent attention to detail
  1. Experience with 16nm Finfet or smaller process nodes
  2. Experience with design implementation of GPU blocks and standard industry standard tools is advantageous
  3. Ability to read Verilog is preferred
  4. Hands-on experience with clock tree synthesis (CTS)

Sign-off experience with reliability, signal integrity, noise, timing, power, physical and DFM closure is an added advantage

Dice Id : xorca001
Position Id : 6758071
Originally Posted : 3 months ago
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