ASIC/FPGA Verification Engineer (5220)

"ASIC VERIFICATION" AND "FPGA" AND "SYSTEM VERILOG" AND "UVM" AND "PYTHON"
Full Time, Contract W2
Depends On Experience
Telecommuting not available Travel not required

Job Description

ASIC/FPGA Verification Engineer

Seeking design verification engineer for verification of FPGA design. 

Required:

• 1 - 2 years of experience in System Verilog.  UVM preferred but OVM or VMM acceptable.

• Able to maintain scripts written in Python.  Perl, Ruby experience is ok.

• 2 - 3 projects with coverage closure and test debug.  Experience achieving functional coverage and code coverage.

Posted By

Brittney Goodwin

2105 S. Bascom ave, #135 Campbell, CA, 95008

Contact
Dice Id : 10123851
Position Id : 5220
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