ASIC/FPGA Verification Engineer
Seeking design verification engineer for verification of FPGA design.
• 1 - 2 years of experience in System Verilog. UVM preferred but OVM or VMM acceptable.
• Able to maintain scripts written in Python. Perl, Ruby experience is ok.
• 2 - 3 projects with coverage closure and test debug. Experience achieving functional coverage and code coverage.
2105 S. Bascom ave, #135 Campbell, CA, 95008Contact