ASIC Design Engineer (Contract)

Analog circuits, Cadence, Communication skills, DSP, ICS, Mixed-signal integrated circuit, SDF, Self motivated, Simulation, Software, Software development, SpyGlass, SystemVerilog, Verilog, Behavioral modeling
Contract W2, Contract Independent, 12 Months
$80 - $90

Job Description



  • Experience with high performance digital blocks for mixed signal ICs.
  • Proficient with Verilog-HDL & System Verilog coding.
  • Understanding of high speed DSP applications, clock domain crossing will be helpful.
  • Understanding & exposure to verilog AMS simulation, experience in behavioral models of analog circuit will be plus.
  • Proficient with Cadence tools such as NCVerilog, NCSIM, Simvision. Experience with linting tools (i.e Spyglass) will be helpful.
  • Exposure to SDF annotated simulations with good understanding of parasitic delays and timings is required.
  • Independent, self-motivated with good analytical & communication skills.


Dice Id : 10308440
Position Id : 6777022
Originally Posted : 6 months ago
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