Visa sponsorship or transfers not available.
Our client is looking for highly talented, motivated researchers to lead and impact state of the art research and development in the area of reconfigurable computing. This position will lead research in algorithm development for custom internal tools which target FPGA and ASIC front end design. These tools solve challenging problems in hardware security, high level abstraction for hardware design, and machine learning acceleration for critical systems. Realize effectiveness of solutions on physical FPGAs and custom ASIC fabrication. Lead research, propose major innovations, collaborate with peers within the group and across the company, publish results in top tier conferences, and contribute to or lead proposals.
This group is a leader in disrupting and advancing the fields of front-end ASIC and FPGA design, computer architecture, and EDA tools. As an applied research lab, our work spans the creation and maturation of ideas from academic conception to applied research prototypes.
We are looking for highly talented, motivated developers to perform research and development in the area of CAD tools for ASIC and FPGA hardware. This position will collaborate with a high caliber team to create the world’s first customized accelerator for native Fully Homomorphic Encryption (FHE). Research and develop custom EDA tools to perform design space exploration of FHE architectures over performance parameters. Be an active member of a fast-paced ASIC Development team supporting the full life cycle from functional architecture definition to physical implementation, verification, and tape-out. This position will also support efforts in design space exploration for efficient resource utilization and implementation of ASIC and FPGA designs, as well as, evaluation in terms of performance, power, and useability metrics. This position will lead research, propose major innovations, collaborate with peers within the group and across ISI, publish results in top tier conferences, and contribute to or lead proposals.
PhD or MS and equivalent experience in Computer Engineering, Electrical Engineering, or Computer Science required.
Established publication record in computer architecture, ASIC design, Fully Homomorphic Encryption hardware, or hardware security.
3-5 years of experience in Digital Design targeting 22nm or smaller lithography nodes.
Expert level programming in Synthesizable C, VHDL, or Verilog.
Experience interfacing and floor planning with bus (PCIe gen 4/5) memory (DDR3/4), and Single/Differential-ended I/O’s in System on Chip designs.
Expert level user of standard digital design tools such as Cadence Stratus, Genus, and Innovus or Synopsys Synphony, Design Compiler, and IC compiler.
Preferred Job Qualifications:
Experience targeting 12nm or smaller fabrication nodes a significant plus.
Experience with clock tree insertion, scan-chain insertion, and back end layout a plus.
Experience with Cadence JasperGold or Synopsys Formality a plus.
Ability to handle export-controlled data.