ASIC RTL Designer (Contract)

Ansys, Low Power, Low Power Design, communication skills, digital designs, strong communication skills, writing, STA, ASIC, RTL, Synthesis, primetime
Contract W2, Contract Independent, 12 Months
$130 - $145

Job Description

As a Low Power Design Engineer, you will have responsibilities spanning various aspects of low power for a hierarchical multi-voltage SOC design, and work in a cross-functional team with RTL, Synthesis, timing, and physical design engineers. The ideal candidate:

Requirements

- Must have strong concepts of power analysis and intent verification for digital designs. - Must have strong experience writing UPF for multi-voltage hierarchical design at the block and top levels. - Must have experience in power intent verification (preferably using Synopsys’s VCLP), and in a variety of methods to resolve power-intent violations. --Must have experience using Power Analysis tools (preferably using Synopsys’s PrimePower). - Strong understanding of Synthesis and Static Timing Analysis (STA) is highly desirable. - Knowledge of RTL power analysis and reduction software (such as Ansys’s PowerArtist) is preferable. - Must have strong communication skills.

Dice Id : 10308440
Position Id : 7478978
Originally Posted : 3 months ago
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