ASIC RTL Designer

Electrical engineering, Computer vision, MIPI, Mapping, Perl, Physical data model, Python, Design engineering, Digital signal processing, Verilog, Xilinx, FPGA, Hardware, ARM, ASIC, Algorithms, Architecture, Communication skills, DSP, Image processing, C, RTL, Software development, SystemVerilog, AMBA
Contract Independent, 6 Months
$70 - $80

Job Description

As an ASIC/FPGA Design Engineer, you will be responsible for the full design cycle of our image processing hardware blocks. Tasks will include microarchitecture, RTL design, verification and supporting synthesis and physical design teams.


  • BS or MS in Electrical Engineering with 5 or more years of experience
  • Expertise in architecture exploration and mapping algorithms to hardware that meet area, performance and power targets
  • Expertise in digital signal processing, image processing or computer vision highly desirable
  • Excellent Verilog, System Verilog coding skills
  • Working experience with Xilinx-based FPGA platforms highly desirable
  • Working experience with one or more of the following: ARM, AMBA, DSP or MIPI
  • Familiarity with C, C++, Perl or Python programming languages
  • Excellent communication skills


Dice Id : 10308440
Position Id : 6895395
Originally Posted : 3 months ago
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