ASIC Verification Engineer - UVM

ASIC AND VERIFICATION UVM AND SYSTEMVERILOG
Contract W2
Depends On Experience
Telecommuting not available Travel not required

Job Description

ASIC Verification Engineer - UVM

Develop UVM test bench. Build verification environment, build test benches, creates tests and debug tests.  

Required:

• System Verilog

• 2+ years of solid UVM experience

Desired:

• Preferred: SVA (System Verilog Assertions) experience

Posted By

Brittney Goodwin

2105 S. Bascom ave, #135 Campbell, CA, 95008

Contact
Dice Id : 10123851
Position Id : 5251
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