ASIC design Engineer

Lint, CDC, design-for-test,power aware synthesis, formal equivalence checks,static timing analysis,System Verilog based test environment
Full Time
130k$
Telecommuting not available Travel not required

Job Description


SOC integration and IP delivery support. RTL design rule checks such as Lint, CDC, design-for-test. Power aware synthesis, formal equivalence checks, and static timing analysis. Design verification using System Verilog based test environment. Modification/optimization of flow automation scripts.

 

5+ years experience with ASIC design including architecture, verification of integrated systems, RTL design, synthesis, timing closure, DFT, and hands-on experience running associated industry standard CAE tools

Posted By

Akshay Rao

3013 Fountainview St, Suite 180 Houston, NJ, 77057

Contact
Dice Id : 10481584
Position Id : 647889
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