SOC integration and IP delivery support. RTL design rule checks such as Lint, CDC, design-for-test. Power aware synthesis, formal equivalence checks, and static timing analysis. Design verification using System Verilog based test environment. Modification/optimization of flow automation scripts.
5+ years experience with ASIC design including architecture, verification of integrated systems, RTL design, synthesis, timing closure, DFT, and hands-on experience running associated industry standard CAE tools
3013 Fountainview St, Suite 180 Houston, NJ, 77057Contact