Application Developer/ASIC Design Verification Sr. Staff Engineer - Phoenix (9909040) Level 2

RTL Design, Verification area, SoC Design Verification, low level HW/SW interaction and debug and multi CPU and debug arch.
Contract W2, Contract Independent, Contract Corp-To-Corp, 6 Months
$50 - $60

Job Description

Hi,

Greetings for the day!

 

Position-Application Developer/ASIC Design Verification Sr. Staff Engineer - Phoenix (9909040) Level 2

Location: Phoenix, AZ

Interview- Phone & Skype

Citizen/ GC and H1B

 

Python Programming Language - Design Verification – Sr. Staff Eng. 4-7yrs of exp. CL8

We´re looking for SoC Design Verification Eng. to provide design verification services for multi CPU/DSP SoC

RESP:

Testbench devel. - System Verilog UVM and C tests

Integration/devel. of C tests/APIs and SW build flow, UVM mailboxes and HW/SW communication components

Integr. of lower level UVM testbenches

Test plan devel.

Power Aware testbench devel. and simulations

Seamless porting between simulation/emulation/prototyping platforms

Regression setup and d

Debug for RTL/Gate Level Netlist/UPF PA sim/Emulation/Proto

Coverage collection and closure

Working w/ cross functional teams (DV/Arch/Design/FW) to identify coverage scope

MIN QUAL:

5+ yrs of exp. in RTL Design and Verification area of which 2+ yrs of exp. in SoC Design Verification and HW/SW verif.

Deep knwl. of System Verilog UVM and vertical testbench integration

Knwl of low level HW/SW interaction and debug and multi CPU and debug arch.

Exp. w/ devel. of fully automated flows

 

Regards,

Navneet kumar

 

Posted By

Vinayak Bahuguna

10 Austin Ave Iselin, NJ, 08830

Dice Id : 10423087a
Position Id : 6559531
Originally Posted : 2 months ago
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