SOC Verification Design Engineer

System Verilog UVM, C Tests, HW/SW communication components, RTL/Gate Level Netlist/UPF PA sim/Emulation/Proto
Contract W2
Depends on Experience
Work from home not available Travel not required

Job Description

Role: SOC Verification Design Engineer

Location : San Francisco Bay Area

Job Responsibilities:


Testbench development - System Verilog UVM and C tests

Integration/development of C tests/APIs and SW build flow

Integration/development of UVM mailboxes and HW/SW communication components

Integration of lower level UVM testbenches

Test plan development

Power Aware testbench development and simulations

Seamless porting between simulation/emulation/prototyping platforms

Regression setup and debug for RTL/Gate Level Netlist/UPF PA sim/Emulation/Proto

Coverage collection and closure

Working with cross functional teams (DV/Arch/Design/FW) to identify coverage scope

Please connect with Ananya at 415 741 9803 or for more details.

Posted By

Ananya Sengupta

4010 Moorpark Ave, Suite 112 San Jose, CA, 95117

Dice Id : 10410924
Position Id : 6092796
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