CPU Logic Design Verification Engineer - 001083

Expertise in Digital Logic Design and verification
Contract W2, 6 Months
Telecommuting not available Travel not required

Job Description

Primary responsibilities –

-            Development and maintenance of testbench infrastructure in UVM
-            Development of emulation-friendly verification components in Verilog
-            Performance verification of IP and CPU power management
-            Development and debug of UVM and assembly level stimulus

 Required skills:

-          Expertise in Digital Logic Design and verification
-          Exceptional verilog coding and hardware development skills (SV, SVA)
-          Experience in building complex UVM testbenches
-          Demonstrate good communication skills, ability to work with multi-discipline and multi-site team.Able to work with minimal supervision and mentoring

 Academic background/experience:

      -          BS/MS EE/CS, 5+ years

 Preferred skills

-        C++ based programming skills
-      Gate level simulation and debug
-      FPGA-based emulation infrastructure development skills

Posted By

Woody Arnold

4518 Seaboard Lane Fort Collins, CO, 80525

Dice Id : 10110992
Position Id : 690639
Have a Job? Post it

Similar Positions

Analog IC Design Engineer.
  • Technical Link
  • San Jose, CA
Verification Engineer
  • Radiansys, Inc.
  • Santa Clara, CA
Hardware Design Engineer
  • Redfish Technology
  • Campbell, CA
Design Engineer
  • Innovative Logic Inc.
  • Menlo Park, CA
ASIC Design Engineer
  • Ambarella Inc.
  • Santa Clara, CA
ASIC Verification Engineer
  • PerfectVIPs Inc.
  • San Jose, CA
RTL Design Engineer
  • Wipro Ltd.
  • Mountain View, CA