-- Demonstrate experience in Parasitic Extraction domain using industry standard tools (StarRC and/or Quantus)
-- Custom/Analog Parasitic Extraction flow experience using industry standard LVS runset verification (ICV and Calibre)
-- Familiarity with layout and/or schematic entry tools such as Cadence Virtuoso and Synopsys Custom Designer.
-- Demonstrate experience in semiconductor device physics, models and technology scaling.
-- Demonstrate familiarity in industry standard CAD tools/flows for digital and/or analog design.
-- Demonstrate experience with software development/programming in high-level languages (e.g. C/C++, TCL, Perl, Python)
-- Demonstrate experience working on with UNIX/Linux platforms.
-- Ability to work remotely, communicate and interact closely with team members.
-- Demonstrate good collaboration skills while sharing development tasks.
• -- Masters degree in Electrical Engineering or Computer Engineering with
• -- 4+ years of experience in Parasitic Extraction domain with exposure to industry standard LVS & extraction tools, VLSI design and execution.