San Diego, CA 92121
12 Months (possible extension)
DFT Engineer position responsible for implementing advanced DFT/DFD/DFM (design for test/debug/manufacturability) techniques for high performance CPU. The position will involve test insertion, vector development and validation and silicon debug.
10+ years experience in the following areas: -DFT/DFD/DFM techniques for complex SoCs - Fault modeling Stuck-at, Transition, Path Delay, IDDQ, and other models -Scan Insertion, ATPG, Scan Compression, At-speed Testing - Scan Insertion using DFT Compiler or equivalent -Exposure to industry standard ATPG tools like Mentor TestKompress, Synopsys TetraMax, Cadence Encounter Test -Industry standard simulation tools such as VCS, Questasim, NC Verilog -Scripting in Perl and Tcl -Exposure to SoC design and test for mobile market applications.
Experience with LVmemBIST or Synopsys STAR BIST -Silicon bring-up, debug, and validation of DFT features on ATE -Implementation of DFT/DFD/DFM techniques for high performance CPU -Work with design teams to improve low coverage on designs to desired target -Generate ATE patterns and work with Test Engineers during pattern bring up and debug.
Bachelor s Electrical Engineering Preferred: Master's, Electrical Engineering or equivalent experience.