Design Verification Engineer

UVM Design Verification
Full Time
Depends On Experience
Travel not required

Job Description

Job Description:

    • Create verification plans for both block level and SoC level verification
    • Create testbenches in SystemVerilog with OVM/UVM
    • Utilize advanced verification techniques
    • Write tools and scripts in Perl and other script languages to enhance the verification process

Qualifications and requirements:

    • BS, MS or PhD in computer science or engineering
    • Experience with SystemVerilog and OVM/UVM
    • Experience with one or more simulators from the major EDA suppliers (Cadence, Mentor or Synopsys)
    • Experience with standard IP blocks and protocols such as Ethernet, TCP/IP, IPSec, iSCSI, DDR3, PCIe
    • Experience with advanced verification techniques like constrained random generation, functional coverage, assertions and formal verifiers
    • Experience with tools for regression management, configuration management and bug tracking
    • Good software skills in object oriented programming (OOP), C, C++, Perl, csh
    • Good problem solving
Dice Id : 10121377
Position Id : 607874
Originally Posted : 7 years ago
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