Design Verification Engineer

System Verilog, UVM, Python, GPU
Full Time
Depends On Experience
Travel not required

Job Description

Job Title: Design Verification Engineer (Job Id: 288344)

Location: San Jose, CA

Duration: 6+ Months



  • As a Design Verification Engineer you will contribute to the functional verification of GPU Subsystems such as Shader, Texture, and Memory Systems.



  • Triage regression failures and make testbench updates
  • Debug functional errors in RTL model using simulation and debug tools
  • Maintain efficient and clean regression status
  • Develop Scalable SystemVerilog/UVM testbenches for unit level and/or Cluster level verification
  • Review Architecture and Micro-Architecture specifications
  • Closely work with Architects and RTL designers
  • Define, maintain and execute unit level and/or Cluster level verification testplans
  • Generate and run Testcases on logic simulation models
  • Code Functional coverage models and System Verilog assertions
  • Drive Functional Coverage and Code coverage to closure
  • Integrate C++ reference model into Scoreboards



  • 5 + year’s industry experience in a design verification role
  • Proficient in System Verilog/UVM/OVM, OOP/C++
  • Knowledge of GPU, experience with Shader, Texture, or Memory System a plus
  • Experience with code coverage and functional coverage driven verification methodology
  • Experience in creating, running and debugging of SystemVerilog/UVM constraint-random Testbench
  • Excellent working knowledge of scripting languages such as Python or Perl
  • Understanding of micro-architecture, logic design, FSMs, arithmetic datapath pipelines
  • Strong functional verification experience including Test planning, Testbench Architecture, Test/Coverage Model/Assertion Development
  • Strong debugging skills
  • Strong programming skills with good understanding of algorithms and data structures
  • Good verbal and written communication skills


Mahesh Khurpe


Xoriant Corporation

Xoriant is an equal opportunity employer. No person shall be excluded from consideration for employment because of race, ethnicity, religion, caste, gender, gender identity, sexual orientation, marital status, national origin, age, disability or veteran status. 

Posted By

Mahesh Khurpe

Dice Id : xorca001
Position Id : 111719
Originally Posted : 3 years ago
Have a Job? Post it

Similar Positions

ASIC Test Engineer - San Jose, CA
  • Vimerse Infotech Inc
  • San Jose, CA
Design Verification Engineer
  • Best High Technologies
  • Santa Clara, CA
Hardware Engineer II
  • Apex Systems
  • Menlo Park, CA
Hardware Design Engineer
  • Trimble, Inc.
  • Sunnyvale, CA
High Speed Design Engineer
  • Mainz Brady Group
  • Fremont, CA
Hardware Engineer
  • Vertisystem Inc.
  • Menlo Park, CA
DFT engineer Santa Clara, CA or Hudson, MA
  • Canvendor Inc
  • Santa Clara, CA
Sr DFT Engineer
  • Synapse Design
  • San Jose, CA
Sr Design Verification Engineer
  • Radiansys, Inc.
  • Menlo Park, CA
Hardware Bluetooth, WiFi Test Engineer
  • OSI Engineering, Inc.
  • San Jose, CA
ASIC Tester
  • Cloudbourne Global Inc
  • San Jose, CA
Design verification engineer_Sunnyvale, CA
  • Arminus Software LLC
  • Sunnyvale, CA
RTL Design Engineer
  • Innovative Logic Inc.
  • San Jose, CA
SoC Design Verification - ARM SOC
  • Eworld Solutions
  • Santa Clara, CA