Design Verification Engineer

System Verilog, UVM, Python, GPU
Full Time
Depends On Experience
Travel not required

Job Description

Job Title: Design Verification Engineer (Job Id: 288344)

Location: San Jose, CA

Duration: 6+ Months

 

Description

  • As a Design Verification Engineer you will contribute to the functional verification of GPU Subsystems such as Shader, Texture, and Memory Systems.

 

Responsibilities:

  • Triage regression failures and make testbench updates
  • Debug functional errors in RTL model using simulation and debug tools
  • Maintain efficient and clean regression status
  • Develop Scalable SystemVerilog/UVM testbenches for unit level and/or Cluster level verification
  • Review Architecture and Micro-Architecture specifications
  • Closely work with Architects and RTL designers
  • Define, maintain and execute unit level and/or Cluster level verification testplans
  • Generate and run Testcases on logic simulation models
  • Code Functional coverage models and System Verilog assertions
  • Drive Functional Coverage and Code coverage to closure
  • Integrate C++ reference model into Scoreboards

 

Requirements

  • 5 + year’s industry experience in a design verification role
  • Proficient in System Verilog/UVM/OVM, OOP/C++
  • Knowledge of GPU, experience with Shader, Texture, or Memory System a plus
  • Experience with code coverage and functional coverage driven verification methodology
  • Experience in creating, running and debugging of SystemVerilog/UVM constraint-random Testbench
  • Excellent working knowledge of scripting languages such as Python or Perl
  • Understanding of micro-architecture, logic design, FSMs, arithmetic datapath pipelines
  • Strong functional verification experience including Test planning, Testbench Architecture, Test/Coverage Model/Assertion Development
  • Strong debugging skills
  • Strong programming skills with good understanding of algorithms and data structures
  • Good verbal and written communication skills

Regards,

Mahesh Khurpe

408-550-1251

Xoriant Corporation

Xoriant is an equal opportunity employer. No person shall be excluded from consideration for employment because of race, ethnicity, religion, caste, gender, gender identity, sexual orientation, marital status, national origin, age, disability or veteran status. 

Dice Id : xorca001
Position Id : 111719
Originally Posted : 4 years ago
Have a Job? Post it

Similar Positions

Design Verification Engineer
  • Mirafra Inc
  • San Jose, CA, USA
ASIC Design Verification Staff Engineer
  • American Cybersystems, Inc.
  • Menlo Park, CA, USA
ASIC Design Engineer
  • Technical Link
  • San Jose, CA, USA
ASIC Verification Engineer
  • Apidel Technologies
  • Santa Clara, CA, USA
Job Opportunity - ASIC Verification Engineer - Santa Clara, California
  • Infobahn Softworld Inc.
  • Santa Clara, CA, USA
Graphics Verification Engineer
  • Xpeerant Incorporated
  • Santa Clara, CA, USA
Design Verification Engineer
  • Net2Source Inc.
  • San Jose, CA, USA
Principal/Senior Design Verification Engineer
  • InterSources Inc.
  • Santa Clara, CA, USA
SOC Design Verification Engineer at San Jose CA
  • Mirafra Inc
  • San Jose, CA, USA