Design Verification and Gate Level Simulation Principal Engineer

Python, Verification, Stimulation, RTL
Contract Corp-To-Corp, Contract W2, 6+ Months

Job Description

Job Title: Design Verification and Gate Level Simulation Principal Engineer

Location: Onsite locations - San Jose CA, Austin TX & Phoenix AZ

Contract: C2C / W2

MUST Have Skills:

  • The ideal candidate should have 3-5+ years of Gate-Level Simulation experience.
  • Expertise with debugging in Best/Worst SDF with min/max corner simulations.
  • Understanding of various timing violations and identifying them as waiver or real netlist issues by working closely with design and architecture teams.
  • Experience with timing constraints and multi clock domain design
  • Run tests on RTL and Gate Level Netlists, debug failures to root cause, and recommend fixes.
  • Engage with the team to drive continuous improvement to the verification env to find more bugs and improve coverage
  • Work as a team to grow together. Mentor and coach junior team members
  • Power-Aware simulation experience is desirable.

Additional Job Details:

1 - C (Programming Language) (P3 - Advanced) |

2 - C++ Programming Language (P3 - Advanced) |

3 - Industry X IOT Applications (P3 - Advanced) |

4 - PERL Scripts (P3 - Advanced)

Please share resume to

Dice Id : 91123676
Position Id : 2022-6621
Originally Posted : 2 months ago
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