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Looking for a candidate to join a team of expert mixed-signal ASIC designers involved in design, verification, and implementation of advanced signal processing algorithms for the physical layer of high speed Serdes at speeds of 50G+. The types of algorithms that will be implemented include: PAM & other higher order modulation, single/multi-input adaptive equalizers/cancellers, single/multi-dimensioned FEC, digital filters, and interface/integration with analog functions and analysis and compensation for analog circuit non-linearities.
Develop channel models and run simulations to help define Serdes architecture
Define and document signal processing block requirements, architecture and lab test plan
Develop bit-exact MATLAB and C/C++ system models for simulation and verification
Develop and run system level simulation suites of the Serdes to evaluate architectural tradeoffs
Work with design team to perform vector matching verification with RTL simulations
Develop, test and debug firmware associated with physical layer functionality
Lab testing and debug of Serdes
Documentation/application note development and customer support
Support marketing group with customer meetings and collateral
M.S.E.E. with 6 years experience is typical
Expert knowledge in Communication Theory
Expert knowledge in Digital Signal Processing algorithms
Working knowledge of Analog circuit behavior
Working knowledge of Transmission line theory and s-parameter
Expert in MATLAB, C/C++ programming
Good hands-on skills in the lab
Experience in designing high-speed Clock and Data Recovery (CDR) PLLs is a very big plus.
RTL coding is a plus
Knowledge of IEEE 802.3 10G/25G/50G Serdes is a plus