Mask Designer (Cadence virtuoso, Chip Layout Development, C++, TCL, Perl, Python)

Layout, Tcl, Design engineering, C++, Virtuoso, Perl, Python, schematics, Cadence, Silicon-package
Contract W2, 6 Months
Depends on Experience
Work from home available

Job Description

This position is within Advanced Design Technology and Solutions - working to design Assembly Test chips, use to understand various Silicon-package interactions. The candidate should be able to perform a Variety of Technical tasks associated with all phases of chip Iayout development, up to and including Unit and Chip-Level Iayout mask design and layout verification. Must possess strong Iayout design skills - with expertise with Cadence Virtuoso and Genesys, and be able to work independently after receiving inputs form the test chip design engineer. The candidate should develop and maintain Iayout schedules. Must be able to plan, draw, assemble and verify complex layouts or units by utilizing design rule books. Must be able to understand schematics and convert to layout. Top Skills/Tools: Experienced DA with extensive experience in environment setup and automation for Cadence virtuoso tools
Scripting: - TCL, Perl, Python
Knowledge of Virtuoso Layout Tool, Library Management * For layout automation purpose in Virtuoso, it used to be skill
SKILL coding
C++ is preference Two year Technical degree and 8+ years of directly related experience

Dice Id : 10509960
Position Id : 21653AZ
Originally Posted : 5 months ago
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