· Hands-on responsibility from synthesis to place and route of a complex GPU block through signoff flows including timing and physical verification
· Synthesis, Floor plan, Place & Route in chip-level and hierarchical physical implementation environment
· Running MBIST and DFT insertion into block, understanding impact of MBIST/Scan and debug logic is desirable
· Interact with RTL counterpart to resolve design issues pertaining to block closure
· Ability to work independently to make good technical trade-offs between power, area, timing
· Ability to work well in a team setting
· Assist design leads to own and drive critical design issues to closure.
Requirements - Job Requirements:
· MSEE or BSEE with 7+ years relevant experience preferred (or equivalent education and experience)
· Strong communication skills, team player working in collaborative work environment, discipline and planning; ability to execute with high quality deliverables is a must
· Solid understanding and working knowledge of the GPU/ASIC design flow with solid experience in taping out designs
· Experience with 16nm finfet or smaller process nodes is strongly preferred
· Hands-on experience with synthesis, block and full chip implementation with the latest industry P&R/STA flows and tools
· Solid hands on experience with clock tree synthesis (CTS), multi-voltage and multi-clock designs
· Strong working knowledge of formal equivalency checks, LP checks, timing constraints, UPF.
· Experience in block level floor-planning, implementing power grid and area/congestion optimization
· Sign-off experience with reliability, signal integrity, noise, timing, power, physical and DFM closure is an added advantage
· Strong scripting/programming skills in Tcl, Perl, Shell, and/or Python is strongly preferred.
· Synopsys DC/ICC2, Fusion Compiler knowledge is required.
· Solid understanding of Electrical Engineering fundamentals, analytical aptitude and excellent attention to detail