Physical Design Engineer

physical design, 7 nm finfet, timing analysis, synthesis, floorplann, clocking, perl, tcl, unix, shelll, python
Contract W2, Contract Independent
$80 - $100
Work from home not available Travel not required

Job Description

Qualification/Experience/Skills Required:

  • Hands-on tape-out experience performing timing and physical verification closure on 7nm FinFET TSMC process or similar technology nodes
  • Hands-on experience with block level physical design (synthesis to GDS)
  • Experience with SoC level integration (multiple blocks, SoC floorplan, clocking and timing analysis) preferred
  • Expertise on Cadence (Innovus) P&R, Synopsys PrimeTime/StarRC, Ansys Redhawk and Mentor Graphics Caliber EDA tools
  • Proficiency in scripting language, such as, Perl, Tcl, Unix Shell, Python
  • Solid engineering understanding of the underlying concepts of IC design, implementation flows and methodologies for deep submicron design

Roles & Responsibilities:

  • Block level synthesis and physical design activities for one or more blocks.
  • Block level physical design includes floorplan, power plan, placement, CTS, timing analysis and route.
  • Signoff timing and physical verification closure.
  • As part of the block level implementation, you will need to ensure the floorplan is optimal, congestion issues are resolved, and timing is under control at every stage from placement, CTS and route stages
  • Signoff tasks include Timing closure with crosstalk and OCV under Multi-Mode Multi-corner conditions, Noise signoff, Physical verification including LVS, DRC, Antenna and IR closure.
  • Flow development/automation

Posted By

Ashik Kumar

1731 Technology Br., Suite 550 San Jose, CA, 95110

Contact
Dice Id : 10195273
Position Id : 448
Originally Posted : 4 months ago
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