Physical Design Engineer

FINFET, ICC, SYNOPSYS, PHYSICAL DESIGN, TIMING CLOSURE
Contract W2, 12 Months
$80 - $90
Work from home available Travel not required

Job Description

Requirements

BSEE, Computer Engineer or comparable and 3 + years of experience

Solid understanding and working knowledge of the SOC/ASIC/GPU/CPU design flow with some experience in taping out designs

Hands-on experience with synthesis, block and full chip implementation with the latest industry P&R/STA flows and tools

Experience in block level floor-planning, implementing power grid and power/area/performance optimization

Strong scripting/programming skills in Tcl, Perl, Shell, and/or Python

Solid understanding of Electrical Engineering fundamentals, analytical aptitude and excellent attention to detail

Strong communication skills, team player working in collaborative work environment, discipline and planning; ability to execute with high quality deliverables is a must

 

Preferred candidate will possess the following:

Experience with 16nm Finfet or smaller process nodes

Experience with design implementation of GPU blocks and standard industry standard tools is advantageous

Ability to read Verilog is preferred

Hands-on experience with clock tree synthesis (CTS)

Sign-off experience with reliability, signal integrity, noise, timing, power, physical and DFM closure is an added advantage

Dice Id : xorca001
Position Id : 5967988
Originally Posted : 1 year ago
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