Physical Design Engineer

signoff, pnr, synoplsys, icc, Calibre, sta, floorplan
Full Time
Depends on Experience

Job Description

Title:                    Physical Design Engineer (Sr.)

Locations:           Santa Clara, CA

Duration:           Fulltime

Experience:     5+ years



  • Participate and Provide inputs for large networking chips Physical Design Methodology
  • Work on Blocks with IO, PLL and Efuse macros and take it through complete signoff
  • Work on closing final DRCs, manually or with scripts
  • Work on AP routing for complete chip
  • Manage chip level integration and physical verification

Must have Skills:

  • MSEE/MSCS/MSCE degree or BSEE/BSCS/BSCE degree
  • Experience with advanced technology like 7nm, 5nm in terms of doing large chips physical design
  • Expertise developing flow for PD using innovas/synopsys/cadence tool chains
  • Expertise in signoff (timing, IR, EM, Verification) for tapeout quality GDS
  • Guide and manage PD team members
  • Participate in pre-sales activities
  • Work with teams across different locations

Good to have skills:

  • Scripting tools like Tcl, Shel
Dice Id : 10102143
Position Id : 7102905
Originally Posted : 2 months ago
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