Position: RFIC or Layout Engineer
Location: San Diego, CA or Cupertino, CA or Austin, TX
Duration: 12 months Contract on W2
In this role, you will work closely with the RFIC design team to layout and verify custom RF and Analog IP for complex SoC products.
Experience in custom RF/Analog layout with extensive knowledge of deep sub-micron CMOS (7nm , 28nm, FinFET, etc.)
Knowledgable in layout techniques for device matching, minimizing parasitics, RF shielding, and high frequency routing
Solid understanding of RC delay, electromigration, and coupling
Understanding of guard rings, DNW, PN junctions, and advanced process effects such as LOD, WPE, etc.
High level proficiency in interpretation of CALIBRE DRC, ERC, LVS, etc.
Knowledge of CADENCE layout tools
Excellent communication skills and able to work with cross-functional teams
You would also have the following, if you're more experienced:
Capability to lead other layout engineers for top-level integration
Ability to recognize failure prone circuit and layout structures and proactively work with circuit designers for the best approach to resolve problems
Scripting skills in PERL or SKILL are a plus, but not required
As a RF layout engineer, you will be responsible for